Field of the Invention
The present invention relates to an electrostatic discharge protection circuit, and in particular it relates to an electrostatic discharge protection circuit with a voltage detection circuit and an electrostatic driving circuit.
Description of the Related Art
Electrostatic discharge (ESD) and electrical overstress (EOS) are two major contributors to the damage of electrical component and electrical system, which would cause temporary or permanent damage to electrical systems and their components. These unexpected electrical stresses will cause damage to electrical components, cause the integrated circuits (IC) to work abnormally, and cause the electronic product to malfunction gradually.
Damage inflicted by electrostatic discharge to a product may be caused by a wide range of factors, which are often not easily avoidable. Static electricity can be accumulated during the manufacturing, assembling, testing, and storage processes; it is also accumulated in the human body, instrumentation, and storage equipment, especially in the electronic components themselves. Being unaware of the static electricity, humans become a transfer gateway for static electricity to discharge when they come in contact with electronic elements, thereby causing damage to the electronic systems and components.
FIG. 1 is a schematic diagram illustrating an electrostatic discharge protection circuit of the prior art. As shown in FIG. 1, the electrostatic discharge protection circuit 100 is arranged to protect other circuits from ESD damage. The electrostatic discharge protection circuit 100 includes a time-constant circuit 110, an inverter 120 and an NMOS transistor N2. The time-constant circuit 110 is constituted by the resistor RA and the capacitor CA, and arranged to provide a time constant. Moreover, the drain D, the source S and the gate G of the NMOS transistor N2 are coupled to the pin 130, the ground and the output terminal of the inverter 120, respectively. When an ESD event occurs at the pin 130, the time-constant circuit 110 induces a low voltage to be applied to the input terminal of the inverter 120, such that a high voltage is applied to the gate G of the NMOS transistor N2 to turn on the NMOS transistor N2, and a discharge path is formed between the pin 130 and the ground. At the same time, the ESD current can be discharged by the NMOS transistor N2 which is turned on.
However, when the circuits protected by the electrostatic discharge protection circuit 100 are operating or are undergoing a latch-up test, EOS event might take place and cause the latch-up phenomenon in the circuits protected by the electrostatic discharge protection circuit 100. Therefore, the prior electrostatic discharge protection circuit 100 is not capable of providing EOS and latch-up immunity.